The present invention relates to the field of integrated circuit design and, in particular, to a scheme for eliminating the presence of negative and non-monotonic delay artifacts in timing characterizations/analyses of circuit blocks.
Modern integrated circuit design is usually carried out by engineers with the assistance of computer aided design (CAD) tools. Using CAD tools such as ECAD, HSPICE, Verilog, etc., the designers access a cell library to construct the target integrated circuit using the various basic logic cells available in the library. Usually, each cell in the library represents a previously designed and tested logic element.
For example, each cell may be first designed using the same CAD tools, which then predict the response of the designed cell to one or more input signals and in particular predict the propagation delays of output signals relative to various input signals. Based on this design, the cell may be fabricated on a semiconductor substrate, e.g., silicon, etc., and then packaged. Thereafter, real input signals may be applied to the packaged cell to measure the actual propagation delays of the output signals. By learning the actual operating characteristics of various cells in this way, the designers (or others) can recharacterize the logic cell(s) and/or recalibrate elements of the CAD system until the predicted propagation delays match the actual propagation delays. In this way, the library cells become useful design elements for constructing larger integrated circuits, the performance of which can be predicted based on the timing data that characterizes the library cells.
One way of determining the overall timing characteristics of an integrated circuit under test is through a report generated by a computer-based timing analysis tool. Such tools are often used to provide delay information for different circuit paths of the integrated circuit of interest. Such a report often provides raw data regarding the different paths through the integrated circuit, along with their associated delays, that can be used to compute the different timing characteristics, for example setup and hold times for inputs, and propagation delays for outputs.
However, such tools require that all the cells used in the design be characterized using the same threshold value. The conventional characterization tools used for timing characterization use a single common threshold value for all transitions for each cell in the library. By default, most conventional tools set this common threshold at one-half of the supply voltage, commonly designated as Vcc/2.
By way of example, consider the logic element chain 10 shown in FIG. 1. There are three logic elements in the chain: an input inverter 12, a buffer 14 and an output inverter 16. Input signals applied to the input of inverter 12 are logically inverted at the output thereof after a propagation delay Tpdxe2x80x94inv1. Subsequently, this signal becomes an input signal to buffer 14, which provides an output signal to inverter 16 after a propagation delay Tpdxe2x80x94buf. Finally, output inverter 16 provides an output signal that is the logical inverse of the input received from buffer 14 after a propagation delay Tpdxe2x80x94inv2. Conventional timing analysis tools require that the voltage levels at which input and output signals of each of these devices switch be equal.
To meet the above requirement, the characterization/analysis tools use a single common threshold for all transitions on the inputs and the outputs, which is usually set to Vcc/2. Having such a single common threshold gives rise to problems, however, when one considers the actual behavior of devices such as inverters 12 and 16 and buffer 14. It may be the case that, in practice, the true input threshold of buffer 14 is below Vcc/2 for a rising input signal. That is, a voltage of less than Vcc/2 at the input of buffer 14 may cause the output thereof to begin switching logic states. Similarly, for a falling input signal, the buffer 14 may have a true threshold that is above Vcc/2.
Either of the above conditions can give rise to so-called xe2x80x9cnegative delaysxe2x80x9d, or more generally, non-monotonic delays. That is, the artifacts caused by the use of a single common switching threshold may be manifest as overly optimistic propagation delays that do not resemble those that will be experienced in real-world circuits. FIG. 2 illustrates an example of such a negative delay. In the top illustration, an input signal is shown for an arbitrary logic element (e.g., buffer 14), while in the lower illustration an output signal of that logic element is shown. The input signal has some rise time (e.g., a period of time over which the signal rises from one voltage level, say 0 V, to another voltage level, say Vcc), as does the output signal. By convention, those of ordinary skill in the art refer to a period of time over which a signal rises from a lower voltage level to a higher voltage level as a rise time while the period of time over which a signal decreases from a higher voltage level to a lower voltage level is termed a fall time. Input signals and output signals may each have rise or fall times depending upon whether the signals are transitioning to lower or higher voltage levels or vice versa, respectively.
Conventional timing characterization/analysis tools assume that the output signal does not begin switching until the input signal has reached the single, common threshold value, say Vcc/2. The time between the point at which the output signal begins switching and when the logic state of the output signal changes (again, commonly chosen as Vcc/2) is regarded as the propagation delay (Tpd) associated with the logic element. Thus, conventional timing characterization/analysis tools may determine Tpd as the time between the point where the input signal crosses the Vcc/2 threshold and the point where the output signal does likewise. Where, as shown in the illustration, the actual input threshold is below Vcc/2, however, such an analysis leads to a negative Tpd, in as much as the output signal switches (crosses Vcc/2) before the input signal reaches the Vcc/2 level.
Negative delay artifacts such as those illustrated in FIG. 2 can cause problems with the timing analysis, synthesis, and simulation of an integrated circuit and so are undesirable. In the past, designers have been forced to use a limited number of solutions to such problems. For example, efforts at shifting the single common threshold for rise and fall times from Vcc/2 to some other voltage level and observing the results for each logic element have been undertaken by some. This is a trial and error process that does not always produce a satisfactory result, for example because correcting a negative rise time delay for one logic element may result in a negative fall time delay for another. In other cases, designers may treat negative delays as xe2x80x9czero delaysxe2x80x9d, essentially modeling a logic element as having no propagation delay whatsoever, but adding long hold times to the signals associated with those elements. Such characterizations are not only inaccurate, they tend to result in overly conservative characterizations of the device under test and so do not yield desirable results. Moreover, they are not useful for actual timing analyses of the device. What is needed therefore, is a scheme for eliminating negative delays that does not suffer from such drawbacks.
In one embodiment, a timing characterization/analysis of a number of circuit blocks of a library or an integrated circuit, each circuit block having an associated rise threshold value and fall threshold value, is performed using a common rise voltage threshold value equal to a minimum one of the rise threshold values of all the circuit blocks and a common fall threshold value equal to a maximum one of the fall threshold values of all the circuit blocks. The rise threshold value of each of the circuit blocks may be determined through an iterative process in which a new rise threshold is determined for an input corresponding to an output threshold value equal to the previous rise or fall threshold. This iterative process may be repeated until the new rise threshold is within a required tolerance value of the preceding rise threshold. Similarly, the fall threshold value of each of the circuit blocks may be determined through an iterative process in which a new fall threshold is determined for an input corresponding to an output threshold value equal to the previous rise or fall threshold. This iterative process may be repeated until the new fall threshold is within a required tolerance value of the preceding fall threshold.
A rise and fall threshold pair for a library of circuit blocks, each of which have corresponding rise and fall thresholds as determined according to the iterative process may then be selected. In general, any of the above processes may be implemented as computer-readable instructions stored in or recorded on computer-readable media (e.g., CD-ROMs, memories, disk drives, etc.).
In still another embodiment, delay information for a previously characterized set of circuit blocks may be scaled using minimum rise threshold and maximum fall threshold information for the circuit blocks. The delay information for each circuit block may be scaled by adding a time value derived using the minimum rise or maximum fall threshold information for the input and subtracting a time value derived using the minimum rise or maximum fall threshold information for the output.